Efficient implementation of log2(__m256d) in AVX2(AVX2中log2(__m256d)的高效实现)
问题描述
SVML 的 __m256d _mm256_log2_pd (__m256d a)
在 Intel 之外的其他编译器上不可用,他们说它的性能在 AMD 处理器上有缺陷.AVX 中提到了互联网上的一些实现g++-4.8 中缺少日志内在函数 (_mm256_log_ps)? 和 SIMD 数学SSE 和 AVX 的库,但是它们似乎比 AVX2 更 SSE.还有 Agner Fog 的矢量库 ,但它是一个大型图书馆,拥有更多的东西,只是矢量 log2,所以从它的实现来看,很难找出向量 log2 操作的基本部分.
那么有人能解释一下如何有效地为 4 个 double
数字的向量实现 log2()
操作吗?IE.就像 __m256d _mm256_log2_pd (__m256d a)
所做的那样,但可用于其他编译器,并且对 AMD 和 Intel 处理器都相当有效.
在我当前的特定情况下,数字是 0 到 1 之间的概率,对数用于熵计算:P[i] 的所有
.i
的求和的否定*日志(P[i])P[i]
的浮点指数范围很大,因此数字可能接近 0.我不确定准确性,因此会考虑任何以 30 位尾数开头的解决方案,尤其是可调整的解决方案是首选.
这是我到目前为止的实现,基于来自 https:/的更高效系列"/en.wikipedia.org/wiki/Logarithm#Power_series .如何改进?(性能和准确性都需要改进)
到目前为止,我的实现提供了每秒 405 268 490 次操作,并且似乎精确到第 8 位.性能通过以下函数来衡量:
对比
最后是我最好的结果,它在 Ryzen 1800X @3.6GHz 上每秒给出大约 8 亿个对数(每个 4 个对数的 2 亿个向量)单线程,直到尾数的最后几位都是准确的.剧透:看看到底如何将性能提高到每秒 8.7 亿对数.
特殊情况:负数、负无穷大和带有负符号位的 NaN
被视为非常接近 0(导致一些垃圾大的负对数"值).正无穷大和带有正符号位的 NaN
产生大约 1024 的对数.如果您不喜欢特殊情况的处理方式,一种选择是添加代码来检查它们并执行适合您的操作更好的.这会使计算速度变慢.
它结合了查找表方法和一阶多项式,主要在维基百科上进行了描述(链接在代码注释中).我可以在这里分配 8KB 的 L1 缓存(这是每个逻辑核心可用的 16KB L1 缓存的一半),因为对数计算对我来说确实是瓶颈,并且没有更多的东西需要 L1 缓存.
但是,如果您需要更多一级缓存来满足其他需求,您可以通过将 cnLog2TblBits
减少到例如,减少对数算法使用的缓存量5 以降低对数计算精度为代价.
或者为了保持较高的准确度,您可以通过添加以下内容来增加多项式项的数量:
然后在 const __m256d t = _mm256_div_pd(tNum, tDen);
行之后改变 Log2TblPlus()
的尾部:
然后注释//对数的前导整数部分
,其余部分不变.
通常你不需要那么多项,即使是几位表,我只是提供系数和计算以供参考.很可能如果cnLog2TblBits==5
,除了terms012
,你不需要任何东西.但是我还没有做过这样的测量,你需要根据自己的需要试验一下.
显然,您计算的多项式项越少,计算速度就越快.
<小时>编辑:这个问题在什么情况下 AVX2 收集指令会比单独加载数据更快? 表明如果
,您可能会获得性能改进被替换为
对于我的实现,它节省了大约 1.5 个周期,将计算 4 个对数的总周期数从 18 减少到 16.5,因此性能提高到每秒 8.7 亿对数.我将保留当前的实现,因为一旦 CPU 开始正确地执行 gather
操作(像 GPU 一样进行合并),它会更加惯用并且应该会更快.
EDIT2:在 Ryzen CPU 上(但不是在 Intel 上) 你可以通过替换获得更多的加速(大约 0.5 个周期)
与
SVML's __m256d _mm256_log2_pd (__m256d a)
is not available on other compilers than Intel, and they say its performance is handicapped on AMD processors. There are some implementations on the internet referred in AVX log intrinsics (_mm256_log_ps) missing in g++-4.8? and SIMD math libraries for SSE and AVX , however they seem to be more SSE than AVX2. There's also Agner Fog's vector library , however it's a large library having much more stuff that just vector log2, so from the implementation in it it's hard to figure out the essential parts for just the vector log2 operation.
So can someone just explain how to implement log2()
operation for a vector of 4 double
numbers efficiently? I.e. like what __m256d _mm256_log2_pd (__m256d a)
does, but available for other compilers and reasonably efficient for both AMD and Intel processors.
EDIT: In my current specific case, the numbers are probabilities between 0 and 1, and logarithm is used for entropy computation: the negation of sum over all i
of P[i]*log(P[i])
. The range of floating-point exponents for P[i]
is large, so the numbers can be close to 0. I'm not sure about accuracy, so would consider any solution starting with 30 bits of mantissa, especially a tuneable solution is preferred.
EDIT2: here is my implementation so far, based on "More efficient series" from https://en.wikipedia.org/wiki/Logarithm#Power_series . How can it be improved? (both performance and accuracy improvements are desired)
So far my implementation gives 405 268 490 operations per second, and it seems precise till the 8th digit. The performance is measured with the following function:
Comparing to the results of Logarithm in C++ and assembly , the current vector implementation is 4 times faster than std::log2()
and 2.5 times faster than std::log()
.
Specifically, the following approximation formula is used:
Finally here is my best result which on Ryzen 1800X @3.6GHz gives about 0.8 billion of logarithms per second (200 million vectors of 4 logarithms in each) in a single thread, and is accurate till a few last bits in the mantissa. Spoiler: see in the end how to increase performance to 0.87 billion logarithms per second.
Special cases:
Negative numbers, negative infinity and NaN
s with negative sign bit are treated as if they are very close to 0 (result in some garbage large negative "logarithm" values). Positive infinity and NaN
s with positive sign bit result in a logarithm around 1024. If you don't like how special cases are treated, one option is to add code that checks for them and does what suits you better. This will make the computation slower.
It uses a combination of lookup table approach and a 1st degree polynomial, mostly described on Wikipedia (the link is in the code comments). I can afford to allocate 8KB of L1 cache here (which is a half of 16KB L1 cache available per logical core), because logarithm computation is really the bottleneck for me and there is not much more anything that needs L1 cache.
However, if you need more L1 cache for the other needs, you can decrease the amount of cache used by logarithm algorithm by reducing cnLog2TblBits
to e.g. 5 at expense of decreasing the accuracy of logarithm computation.
Or to keep the accuracy high, you can increase the number of polynomial terms by adding:
And then changing the tail of Log2TblPlus()
after line const __m256d t = _mm256_div_pd(tNum, tDen);
:
Then comment // Leading integer part for the logarithm
and the rest unchanged follow.
Normally you don't need that many terms, even for a few-bit table, I just provided the coefficients and computations for reference. It's likely that if cnLog2TblBits==5
, you won't need anything beyond terms012
. But I haven't done such measurements, you need to experiment what suits your needs.
The less polynomial terms you compute, obviously, the faster the computations are.
EDIT: this question In what situation would the AVX2 gather instructions be faster than individually loading the data? suggests that you may get a performance improvement if
is replaced by
For my implementation it saves about 1.5 cycle, reducing the total cycle count to compute 4 logarithms from 18 to 16.5, thus the performance rises to 0.87 billion logarithms per second. I'm leaving the current implementation as is because it's more idiomatic and shoud be faster once the CPUs start doing gather
operations right (with coalescing like GPUs do).
EDIT2: on Ryzen CPU (but not on Intel) you can get a little more speedup (about 0.5 cycle) by replacing
with
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